Phase and Jitter Noise analysis of Phase Locks Loop (PLL) as Frequency Synthesiser

In this paper, we are evaluating the performance of the phase lock loop in the presence of phase noise and jitter noise. We are analysing the performance of PLL in one application of signal processing as frequency synthesiser. All the components of PLL contribute to the noise of the system. Two type of noise are presented that affect the performance of the system that are phase noise and jitter noise. Firstly, the Phase noise is generally used for representing short term random frequency variations of a signal. Non linear oscillators naturally produce high phase noise. Secondly, Jitter is generally used to refer to the time variation of a periodic signal in relation to the clock. The phase and jitter are the critical performance parameter to analysis the performance of the PLL. Simulation Result reveals that the performance of the PLL system is affected more by jitter noise compared to that of phase noise. Extensive simulation result is presented to demonstrate the effectiveness of the proposed techniques.